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1

Special issue on selected papers from NORCHIP 2008

Peeter Ellervee, Gert Jervan

Journal:

Analog Integrated Circuits and Signal Processing

Year:

2010

Language:

english

File:

PDF, 134 KB

english, 2010

2

Research in Digital Design and Test at Tallinn University of Technology

Raimund Ubar,Gert Jervan,Artur Jutman

Journal:

Радиоэлектроника и информатика

Year:

2008

Language:

english

File:

PDF, 587 KB

english, 2008

3

[IEEE 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Baltimore, MD, USA (2017.5.28-2017.5.31)] 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

Azad, Siavoosh Payandeh, Niazmand, Behrad, Janson, Karl, Kogge, Thilo, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

Year:

2017

Language:

english

File:

PDF, 422 KB

english, 2017

4

[IEEE 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) - Lille, France (2018.7.9-2018.7.11)] 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) - AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links

Janson, Karl, Pihlak, Rene, Azad, Siavoosh Payandeh, Niazmand, Behrad, Jervan, Gert, Raik, Jaan

Year:

2018

Language:

english

File:

PDF, 989 KB

english, 2018

5

[IEEE 2018 IEEE International Test Conference in Asia (ITC-Asia) - Harbin (2018.8.15-2018.8.17)] 2018 IEEE International Test Conference in Asia (ITC-Asia) - A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers

Niazmand, Behrad, Payandeh Azad, Siavoosh, Ghasempouri, Tara, Raik, Jaan, Jervan, Gert

Year:

2018

Language:

english

File:

PDF, 750 KB

english, 2018

6

[IEEE 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Miami, FL, USA (2019.7.15-2019.7.17)] 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones

Payandeh Azad, Siavoosh, Tempelmeier, Michael, Jervan, Gert, Sepulveda, Johanna

Year:

2019

Language:

english

File:

PDF, 1007 KB

english, 2019

7

Hybrid BIST optimization using reseeding and test set compaction

Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar

Journal:

Microprocessors and Microsystems

Year:

2008

Language:

english

File:

PDF, 503 KB

english, 2008

8

Guest Editorial

Peeter Ellervee, Gert Jervan

Journal:

Microprocessors and Microsystems

Year:

2010

Language:

english

File:

PDF, 95 KB

english, 2010

9

Test Time Minimization for Hybrid BIST of Core-Based Systems

Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin

Journal:

Journal of Computer Science and Technology

Year:

2006

File:

PDF, 411 KB

2006

10

Hybrid BIST energy minimisation technique for system-on-chip testing

Jervan, G., Peng, Z., Shchenova, T., Ubar, R.

Journal:

IEE Proceedings - Computers and Digital Techniques

Year:

2006

Language:

english

File:

PDF, 459 KB

english, 2006

11

[IEEE Systems (DDECS) - Cottbus, Germany (2011.04.13-2011.04.15)] 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems - Communication modelling and synthesis for NoC-based systems with real-time constraints

Tagel, Mihkel, Ellervee, Peeter, Hollstein, Thomas, Jervan, Gert

Year:

2011

Language:

english

File:

PDF, 1.31 MB

english, 2011

12

[IEEE 2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) - York, United Kingdom (2012.07.9-2012.07.11)] 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) - Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints

Amin, Mohsin, Tagel, Mihkel, Jervan, Gert, Hollstein, Thomas

Year:

2012

Language:

english

File:

PDF, 621 KB

english, 2012

13

[IEEE Comput. Soc 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (3-5 Nov. 2003)] Proceedings. 16th IEEE Symposium on Computer Arithmetic - Hybrid BIST time minimization for core-based systems with STUMPS architecture

Jervan, G., Eles, P., Peng, Z., Ubar, R., Jenihhin, M.

Year:

2003

Language:

english

File:

PDF, 233 KB

english, 2003

14

[IEEE 2009 International Symposium on System-on-Chip - SOC - Tampere, Finland (2009.10.5-2009.10.7)] 2009 International Symposium on System-on-Chip - Scheduling framework for real-time dependable NoC-based systems

Tagel, Mihkel, Ellervee, Peeter, Jervan, Gert

Year:

2009

Language:

english

File:

PDF, 447 KB

english, 2009

15

[IEEE 8th Euromicro Conference on Digital System Design (DSD'05) - Porto, Portugal (30-03 Aug. 2005)] 8th Euromicro Conference on Digital System Design (DSD'05) - Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment

Zhiyuan He,, Jervan, G., Zebo Peng,, Eles, P.

Year:

2005

Language:

english

File:

PDF, 165 KB

english, 2005

16

[IEEE 2008 19th EAEEIE Annual Conference - Tallinn (2008.06.29-2008.07.2)] 2008 19th EAEEIE Annual Conference - A survey of the evolution of the Bologna Process in EIE in Europe

Martins, M.J., Thiriet, J.-M., Bonnaud, O., Hoffmann, M., Robert, M., Benlloch, J., Jervan, G.

Year:

2008

Language:

english

File:

PDF, 102 KB

english, 2008

17

[IEEE 13th Asian Test Symposium - Kenting, Taiwan (15-17 Nov. 2004)] 13th Asian Test Symposium - Hybrid BIST Test Scheduling Based on Defect Probabilities

Zhiyuan He,, Jervan, G., Zebo Peng,, Eles, P.

Year:

2004

Language:

english

File:

PDF, 156 KB

english, 2004

18

[IEEE 2013 NORCHIP - Vilnius, Lithuania (2013.11.11-2013.11.12)] 2013 NORCHIP - Sleep apnea pre-screening on neonates and children with shoe integrated sensors

Leier, Mairo, Jervan, Gert

Year:

2013

Language:

english

File:

PDF, 720 KB

english, 2013

19

[IEEE 2007 IEEE International Conference on Microelectronic Systems Education - San Diego, CA, USA (2007.06.3-2007.06.4)] 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07) - Graduate School in Information and Communication Technologies. Experiences at Tallinn University of Technology

Jervan, Gert, Kruus, Margus, Rustern, Ennu

Year:

2007

Language:

english

File:

PDF, 144 KB

english, 2007

20

[IEEE 2007 International Symposium on Industrial Embedded Systems - Costa da Caparica, Portugal (2007.07.4-2007.07.6)] 2007 International Symposium on Industrial Embedded Systems - Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems

Jervan, Gert, Kruus, Helena, Orasson, Elmet, Ubar, Raimund

Year:

2007

Language:

english

File:

PDF, 4.22 MB

english, 2007

21

[IEEE 2014 25th EAEEIE Annual Conference (EAEEIE) - Cesme, Izmir, Turkey (2014.5.30-2014.6.1)] 2014 25th EAEEIE Annual Conference (EAEEIE) - Teaching modeling in SysML/UML and problems encountered

Kruus, Helena, Robal, Tarmo, Jervan, Gert

Year:

2014

Language:

english

File:

PDF, 365 KB

english, 2014

22

[IEEE 2008 19th EAEEIE Annual Conference - Tallinn (2008.06.29-2008.07.2)] 2008 19th EAEEIE Annual Conference - Introduction of graduate schools in Estonia — impact to the graduate education in ICT

Jervan, Gert, Kruus, Margus, Rustern, Ennu

Year:

2008

Language:

english

File:

PDF, 70 KB

english, 2008

23

[IEEE 2006 NORCHIP - Linkoping, Sweden (2006.11.20-2006.11.21)] 2006 NORCHIP - Hybrid BIST Scheduling for NoC-Based SoCs

Jervan, Gert, Shchenova, Tatjana, Ubar, Raimund

Year:

2006

Language:

english

File:

PDF, 6.04 MB

english, 2006

24

[IEEE 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Lubeck, Germany (2007.08.29-2007.08.31)] 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Hybrid BIST Optimization Using Reseeding and Test Set Compaction

Jervan, Gert, Orasson, Elmet, Kruus, Helena, Ubar, Raimund

Year:

2007

Language:

english

File:

PDF, 538 KB

english, 2007

25

[IEEE Comput. Soc 2002 3rd International Symposium on Quality Electronic Design - San Jose, CA, USA (18-21 March 2002)] Proceedings International Symposium on Quality Electronic Design - A hybrid BIST architecture and its optimization for SoC testing

Jervan, G., Peng, Z., Ubar, R., Kruus, H.

Year:

2002

Language:

english

File:

PDF, 379 KB

english, 2002

26

[IEEE Comput. Soc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Yamanashi, Japan (25-27 Oct. 2000)] Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Test cost minimization for hybrid BIST

Jervan, G., Peng, Z., Ubar, R.

Year:

2000

Language:

english

File:

PDF, 586 KB

english, 2000

27

[IEEE 2014 10th European Workshop on Microelectronics Education (EWME) - Tallinn, Estonia (2014.5.14-2014.5.16)] 10th European Workshop on Microelectronics Education (EWME) - Dependable embedded systems: FP7 KhAI-ERA project experience

Kharchenko, Vyacheslav, Kulanov, Vitaliy, Jervan, Gert

Year:

2014

Language:

english

File:

PDF, 368 KB

english, 2014

28

[IEEE 2012 13th Biennial Baltic Electronics Conference (BEC2012) - Tallinn, Estonia (2012.10.3-2012.10.5)] 2012 13th Biennial Baltic Electronics Conference - Profiling in deeply embedded systems

Moorits, Erkki, Jervan, Gert

Year:

2012

Language:

english

File:

PDF, 74 KB

english, 2012

29

[IEEE Comput. Soc Euromicro Symposium on Digital Systems Design - Warsaw, Poland (4-6 Sept. 2001)] Proceedings Euromicro Symposium on Digital Systems Design - Fast test cost calculation for hybrid BIST in digital systems

Orasson, E., Raidma, R., Ubar, R., Jervan, G., Peng, Z.

Year:

2001

Language:

english

File:

PDF, 734 KB

english, 2001

30

[IEEE 2006 International Biennial Baltic Electronics Conference - Tallinn, Estonia (2006.10.2-2006.10.4)] 2006 International Biennial Baltic Electronics Conference - Optimization of the Store-and-Generate Based Built-in Self-Test

Ubar, R., Jervan, G., Kruus, H., Orasson, E., Aleksejev, I.

Year:

2006

Language:

english

File:

PDF, 4.40 MB

english, 2006

31

[IEEE 2013 24th EAEEIE Annual Conference (EAEEIE 2013) - Chania, Greece (2013.05.30-2013.05.31)] 2013 24th EAEEIE Annual Conference (EAEEIE 2013) - Systems engineering course as a backbone of the computer engineering curricula

Year:

2013

Language:

english

File:

PDF, 336 KB

english, 2013

32

[IEEE 2011 NORCHIP - Lund, Sweden (2011.11.14-2011.11.15)] 2011 NORCHIP - Contention aware scheduling for NoC-based real-time systems

Tagel, Mihkel, Ellervee, Peeter, Hollstein, Thomas, Jervan, Gert

Year:

2011

Language:

english

File:

PDF, 958 KB

english, 2011

33

[IEEE European Test Symposium (ETS'05) - Tallinn, Estonia (22-25 May 2005)] European Test Symposium (ETS'05) - Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment

Ubar, R., Shchenova, T., Jervan, G., Zebo Peng,

Year:

2005

Language:

english

File:

PDF, 240 KB

english, 2005

34

[IEEE ICC 2014 - 2014 IEEE International Conference on Communications - Sydney, Australia (2014.6.10-2014.6.14)] 2014 IEEE International Conference on Communications (ICC) - Respiration signal extraction from photoplethysmogram using pulse wave amplitude variation

Leier, Mairo, Jervan, Gert, Stork, Wilhelm

Year:

2014

Language:

english

File:

PDF, 265 KB

english, 2014

35

[IEEE 2010 OCEANS MTS/IEEE SEATTLE - Seattle, WA (2010.9.20-2010.9.23)] OCEANS 2010 MTS/IEEE SEATTLE - Low resource demanding FOTA method for remote AtoN site equipment

Moorits, E, Jervan, G

Year:

2010

Language:

english

File:

PDF, 628 KB

english, 2010

36

[IEEE 2014 10th European Workshop on Microelectronics Education (EWME) - Tallinn, Estonia (2014.5.14-2014.5.16)] 10th European Workshop on Microelectronics Education (EWME) - SysML in systems engineering course

Kruus, Helena, Robal, Tarmo, Jervan, Gert

Year:

2014

Language:

english

File:

PDF, 308 KB

english, 2014

37

[IEEE 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008) - Hong Kong, China (2008.01.23-2008.01.25)] 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008) - Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

Ubar, Raimund, Devadze, Sergei, Jenihhin, Maksim, Raik, Jaan, Jervan, Gert, Ellervee, Peeter

Year:

2008

Language:

english

File:

PDF, 488 KB

english, 2008

38

[IEEE 2010 12th Biennial Baltic Electronics Conference (BEC2010) - Tallinn, Estonia (2010.10.4-2010.10.6)] 2010 12th Biennial Baltic Electronics Conference - Design space exploration and optimisation for NoC-based timing sensitive systems

Tagel, Mihkel, Ellervee, Peeter, Jervan, Gert

Year:

2010

Language:

english

File:

PDF, 114 KB

english, 2010

39

[IEEE Comput. Soc IEEE International High Level Design Validation and Test Workshop (HLDVT'02) - Cannes, France (27-29 Oct. 2002)] Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. - High-level and hierarchical test sequence generation

Jervan, G., Peng, Z., Goloubeva, O., Reorda, M.S., Violante, M.

Year:

2002

Language:

english

File:

PDF, 623 KB

english, 2002

40

[IEEE Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03 - Xi'an, China (2003.11.19-2003.11.19)] Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03 - Test time minimization for hybrid BIST of core-based systems

Jervan,, Eles,, Peng,, Ubar,, Jenihhin,

Year:

2003

Language:

english

File:

PDF, 334 KB

english, 2003

41

[IEEE 2014 25th EAEEIE Annual Conference (EAEEIE) - Cesme, Izmir, Turkey (2014.5.30-2014.6.1)] 2014 25th EAEEIE Annual Conference (EAEEIE) - Evaluation of SysML software for teaching systems engineering basics

Kruus, Helena, Jervan, Gert

Year:

2014

Language:

english

File:

PDF, 518 KB

english, 2014

42

[IEEE 2008 International Biennial Baltic Electronics Conference (BEC2008) - Tallinn (2008.10.6-2008.10.8)] 2008 11th International Biennial Baltic Electronics Conference - Using Tabu Search for optimization of memory-constrained hybrid BIST

Kruus, Helena, Jervan, Gert, Ubar, Raimund

Year:

2008

Language:

english

File:

PDF, 125 KB

english, 2008

43

System-level optimization of NoC-based timing sensitive systems

Tagel, M, Ellervee, P, Hollstein, T, Jervan, G

Journal:

Estonian Journal of Engineering

Year:

2011

Language:

english

File:

PDF, 398 KB

english, 2011

44

System-level communication synthesis and dependability improvements for Network-on-Chip based systems

Tagel, M, Ellervee, P, Jervan, G

Journal:

Estonian Journal of Engineering

Year:

2010

Language:

english

File:

PDF, 235 KB

english, 2010

45

[IEEE 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC) - Milano, Italy (2014.8.26-2014.8.28)] 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing - Fault-Tolerant Scheduling of Mixed-Critical Applications on Multi-processor Platforms

Bagheri, Mehrdad, Jervan, Gert

Year:

2014

Language:

english

File:

PDF, 408 KB

english, 2014

46

[ACM Press the 9th International Symposium - Vancouver, BC, Canada (2015.09.28-2015.09.30)] Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15 - A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Saltarelli, Pietro, Niazmand, Behrad, Raik, Jaan, Govind, Vineeth, Hollstein, Thomas, Jervan, Gert, Hariharan, Ranganathan

Year:

2015

Language:

english

File:

PDF, 815 KB

english, 2015

47

[IEEE 2014 14th Biennial Baltic Electronic Conference (BEC) - Tallinn, Estonia (2014.10.6-2014.10.8)] 2014 14th Biennial Baltic Electronic Conference (BEC) - Miniaturized wireless monitor for long-term monitoring of newborns

Leier, Mairo, Jervan, Gert

Year:

2014

Language:

english

File:

PDF, 471 KB

english, 2014

48

[IEEE 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) - Milan (2015.8.25-2015.8.29)] 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) - Smart photoplethysmographic sensor for pulse wave registration at different vascular depths

Leier, Mairo, Pilt, Kristjan, Karai, Deniss, Jervan, Gert

Year:

2015

Language:

english

File:

PDF, 3.82 MB

english, 2015

49

[IEEE 2014 14th Biennial Baltic Electronic Conference (BEC) - Tallinn, Estonia (2014.10.6-2014.10.8)] 2014 14th Biennial Baltic Electronic Conference (BEC) - Extended checkers for Logic-Based Distributed Routing in Network-on-Chips

Niazmand, Behrad, Hariharan, Ranganathan, Govind, Vineeth, Jervan, Gert, Hollstein, Thomas, Raik, Jaan

Year:

2014

Language:

english

File:

PDF, 341 KB

english, 2014

50

[IEEE 2015 Euromicro Conference on Digital System Design (DSD) - Madeira, Portugal (2015.8.26-2015.8.28)] 2015 Euromicro Conference on Digital System Design - A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Saltarelli, Pietro, Niazmand, Behrad, Raik, Jaan, Hariharan, Ranganathan, Jervan, Gert, Hollstein, Thomas

Year:

2015

Language:

english

File:

PDF, 1.15 MB

english, 2015

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